Traditionally, wire bonding was used to provide an electrical connection between semiconductor devices and external circuitry. The semiconductor device is diced from the wafer on which it was fabricated and placed face-up in a package. Small wires, typically made of gold or copper, are then welded between bond pads present on the semiconductor device and external leads on the package.
Flip chip technology derives its name from placing the semiconductor device face down in the package. Electrical connections between the semiconductor device and the external leads of the package are made by reflowing conductive solder bumps on the surface of the semiconductor device.
Flip chip technology allows a larger number of electrical connections to be made because the entire area of the semiconductor device can be used for forming bond pads whereas in wire bonding the bond pads are typically formed around the periphery of the semiconductor device. Flip chip technology also facilitates faster electrical connections between the semiconductor device and external circuitry by eliminating the resistance and capacitance associated with wire bonds.
Wafer-level chip-scale package (“WLCSP”) or wafer level package (“WLP”) advances the concept of flip chip by forming the electrical connections directly on the semiconductor device, during fabrication of the semiconductor device. This allows the semiconductor device to be directly mounted to a printed circuit board (“PCB”), thereby eliminating the need for a separate package. The resulting packaged device is similarly sized to the bare semiconductor device. WLCSP implementations benefit from further increases in electrical performance as well as smaller package size. The transition in the industry from solders with lead metallurgy to non-lead metallurgies for WLCSP have resulted in more sensitivity to effects of thermal cycling and sudden mechanical shock for high reliability chip packaging.
Redistribution layer (“RDL”) technology allows older semiconductor device designs, in which the bond pads are located around the periphery of the device, to use WLCSP. RDLs create an electrical path between the bond pads on a semiconductor device and the solder bumps, allowing the solder bumps to be evenly distributed across the entire area of the semiconductor device.
FIG. 1 illustrates a prior art bump on IO structure on a device pad prior to solder bumping, and FIG. 2a illustrates the prior art bump on IO structure of FIG. 1 after solder bump 106 is applied. The device consists of substrate 101, device pad 102 and passivation layer 103. Device pad 102 is a metal material, typically comprising aluminum, copper, or a composite of both. Device pad 102 can be formed using any of several methods commonly known in the industry. Substrate 101 may comprise materials such as Silicon, Gallium Arsenide, Lithium Tantalate, Silicon Germanium or other. For clarity, substrate material will generally be referred to herein as Silicon, but the use thereof should not be interpreted as intending to limit the disclosure to only Silicon based substrates.
Device passivation layer 103 typically comprises a silicon nitride, oxidenitride or the like. Passivation layer 103 is not continuous over the device pad, but rather has defined openings where there is no passivation material, which are individually referred to as a passivation opening. The passivation opening is illustrated in more detail in FIG. 2, which provides a top view of the bump on IO structure of FIG. 1. The passivation opening is normally circular and centered on device pad 102. The passivation opening defines a region in which subsequent metal will be deposited in the WLCSP processing or flip chip packaging processing to make a connection and adhere to the device pad.
The prior art for placing an underlying bump on IO structure, such as that illustrated in FIGS. 1 and 2, consists of forming under bump metal pad (“UBM”) 105 using standard metal deposition methods such as metal plating, metal sputtering, or the like. UBM 105 may comprise any of a number of well known materials, including Ti(W)/Cu; Al/Electroless Ni/Immersion Au; Al/Electroless Ni/PdlAu; AlCu/Electroless Ni/Immersion Au; AlCuSi/Electroless Ni/Immersion Au; and AlSi/Electroless Ni/Immersion Au. Because of the techniques and materials used, UBM 105 can adhere to passivation material 103 and device pad 102, and typically forms a layer of about 1.0 microns or greater. The upper surface of UBM 105 provides a site for solder bump placement and facilitates adherence thereof. In FIGS. 1 and 2, the UBM solder bump site is defined by the opening in polymer 104.
Traditional prior art processes utilize a polymer material consisting of a polyimide, benzocyclobutene (“BCB”) or the like. The thickness of polymer 104 is typically 10 microns or less. Polymer 104 is typically photodefined to create an opening which is normally circular and centered on UBM 105. In this example and in majority of traditional prior art solder bumping structures, the diameter of device pad 102 is greater than or equal to the diameter of UBM 105, resulting in a ratio of 1:1 or greater. In such traditional prior art solder bumping structures, the diameter of the opening in polymer 204 is typically less than the diameter of UBM 105, with a ratio of 0.86:1 or less.
FIGS. 3 and 4 illustrate a cross-sectional view and top view, respectively, of alternative prior art bump on IO structures. In this version of the prior art, the diameter of device pad 302 is less than the diameter of UBM 305, with a typical ratio of 0.43:1. The polymer opening diameter is less than the diameter of UBM 305, with a typical ratio of 0.32:1. The prior art for placing an underlying structure such as that illustrated in FIGS. 3 and 4 consists of placing polymer 304, such as polyimide, benzocyclobutene, polybenzoxazole, derivatives of polybenzoxazole, or the like over an opening in device passivation layer 303 and over device pad 302. The thickness of polymer 304 is typically 10 microns or less. Polymer 304 is then photodefined to create an opening which is normally circular and centered on the device passivation opening, and open to the surface of device pad 302.
At this point in the process, polymer 304 has defined a region that connects to device passivation layer 303, and which falls inside the opening in device passivation layer 303. The open region in polymer 304 is known as the polymer opening. Once the polymer opening is defined, UBM 305 will be deposited via standard methods, such as metal plating, metal sputtering or the like. This process forms UBM 305 such that the bottom of UBM 305 adheres to polymer 304, any exposed passivation portion of device passivation layer 303 between polymer 304 and device pad 302, and device pad 302 itself. The top side of UBM 305 is a defined surface for solder bump placement and adherence.
In this structure and in majority of underlying solder bumping structures, the diameter of device pad 302 is less than the diameter of UBM 305, and typically has a ratio of 0.43:1. This results in a significant overlap of UBM 305 over device pad 302. In addition, the diameter of the opening in polymer 304 is typically less than the diameter of UBM 305, and typically has a ratio of 0.32:1.
FIGS. 5 and 6 are cross-sectional views illustrating an exemplary prior art redistribution layer (“RDL”) underlying structure prior to solder bumping. FIG. 6a is a cross-sectional view illustrating an exemplary prior art RDL underlying structure after solder bump 507 has been applied. FIG. 7 is a top view of the structure illustrated in FIGS. 5 and 6. RDL trace 505 is formed using standard metal deposition methods which are well known in the industry. The RDL trace can be either a single layer of metal or stacked metal layers such as titanium/aluminum/titanium or copper or aluminum or nickel copper or chromium/copper/chromium or other. At the end of RDL trace 505, the metal is typically formed into a circular pattern to become landing pad 505a. Landing pad 505a provides a connection point for subsequent WLCSP or flip chip packaging processing. The landing pad can be a single layer of metal or a stack of metal layers such as aluminum, aluminum/nickel/copper, titanium/aluminum/titanium or copper or nickel/gold/copper or other. Once trace 505 and landing pad 505a have been formed, a photodefineable polymer 2 material 506 is deposited over trace 505 and landing pad 505a. An opening is then defined in the polymer 2 material 506, with the opening located in the center area of landing pad 505a and exposing a portion of landing pad 505a. All polymer 2 material 506 outside of the center of the landing pad remains intact, covering trace 505. The thickness of polymer 2 material 506 is typically 20 microns or less. UBM 507 is formed over polymer 2 material 506 and onto landing pad 505a to create an electrical connection between UBM 507 and landing pad 505a. 
Typically, landing pad 505a has a diameter greater than or equal to the diameter of UBM 507. Traditional landing pad diameter to UBM diameter ratios are 1:1 or greater. The polymer 2 opening diameter to UBM diameter ratio is typically 0.9:1 or greater. FIG. 6a illustrates a typical solder bump on RDL.
The prevailing trend in the semiconductor industry is to shift to processing technologies that employ smaller feature sizes, allowing semiconductor devices to exhibit more functionality. System-on-a-chip (“SoC”) devices are an example of the class of semiconductor devices made possible by smaller feature sizes, and are exemplified by the structures illustrated in FIGS. 3 and 4. Smaller feature sizes, combined with larger functionality, has led to reduced input-output (“IO”) pad sizes, as illustrated by comparing FIGS. 1 and 2 with FIGS. 3 and 4. The final IO pad geometry in WLCSP applications has become significantly smaller than the required solder bump, thereby creating a narrow neck structure between the solder bump and the final IO pad geometry. The narrow neck introduces instability and inconsistency to the solder bumps, further increasing their sensitivity to temperature cycling and sudden mechanical impact shock.